1. Field of the Invention
Exemplary embodiments may generally relate to fin-type field effect transistors (FinFETs), used in small complementary metal oxide semiconductor (CMOS) integrated circuits. Particularly, exemplary embodiments of FinFETs may be formed on bulk silicon wafers, where junction isolation of source/drain (S/D) regions is provided. More particularly, self-aligned dielectric isolation of the body and extensions of the FinFET may be provided.
2. Description of the Related Art
Fin-type field effect transistor (FinFET) technology is the leading contender for 14 nm or smaller complementary metal oxide semiconductor (CMOS) integrated circuits. With FinFETs, the fin structure must be isolated from the substrate wafer by a dielectric to avoid large penalties in leakage, power, and variability. Silicon-on-insulator (SOI) substrates provide a simple solution, however SOI wafer cost and volume availability are detractors to this solution.
There remains a need for a structure and method of making a low-cost FinFET that uses bulk silicon wafers, provides junction isolation of the source/drain (S/D) regions, and provides self-aligned dielectric isolation of the body and extensions of the FinFET.